1. Technical Field
This invention relates generally to switches, and more particularly, but not exclusively, to a system and method for generating a delayed clock output for satisfying requirements of the Reduced Gigabit Media Independent Interface standard (RGMII).
2. Description of the Related Art
Networks, such as local area networks (i.e., LANs) and wide area networks (i.e., WANs, e.g., the Internet), enable a plurality of nodes to communicate with each other. Nodes can include computers, servers, storage devices, mobile devices, PDAs, wireless telephones, etc. Networks can include the nodes themselves, a connecting medium (wired, wireless and/or a combination of wired and wireless), and network switching systems such as routers, hubs and/or switches.
Network switching systems communicate with other nodes in a network via input/output (I/O) interfaces. A conventional I/O interface is the Gigabit Media Independent Interface (GMII) as defined by the Institute of Electrical and Electronics Engineers, Inc. (IEEE) 802.3 specification. Each GMII in a switch requires 25 pins. Accordingly, an 8-port Gigabit Switch requires 200 pins, which takes up a large amount of space.
To reduce the amount of space that the pins take up, the RGMII interface has been defined. RGMII is a reduced pin count interface that can simplify design by reducing the interface pin count from the 24 pins used in the GMII interface to 12. It can lower system cost compared to existing GMII interfaces by reducing the number of layers required to route high density networking solutions. Using RGMII, fewer pins are required for the MAC/switch Application Specific Integrated Circuit (ASIC), which can reduce the MAC/switch cost by enabling smaller die sizes than would be possible with GMII or TBI. However, the RGMII specification calls for a timing delay on both the receive signal and the transmit signal for each port.
Conventionally, to implement the timing delay, a 250 MHz phase locked loop (PLL) is communicatively coupled to a clock divide and align circuit that reduces the clock to 125 MHz and outputs a pair of clock signals, in which one of the pair has a 2 ns delay with respect to the other of the pair. However, a disadvantage of this conventional implementation is that it requires the 250 MHz PLL in addition to a 125 MHz PLL used to generate clock signals for the physical layers, thereby increasing the amount of space required within the switch.
Accordingly, a new system and method are needed that generate a 2 ns delay in a clock signal without increasing the amount of space required within a switch.